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rev. 1.0 december 2010 www.aosmd.com page 1 of 16 AOZ1214 ezbuck 3a? simple buck regulator with linear controller general description the AOZ1214 is a high efficiency, simple to use, buck regulator plus one linear regulator controller optimized for a variety of applications. the AOZ1214 works from a 4.5v to 28v wide input voltage range. the buck regulator provides up to 3a of continuous output current. each output voltage is adjustable down to 0.8v. the buck regulator and ldo can be enabled independently. the AOZ1214 is available in a 4x3 dfn-12 package and can operate over a -40c to +85c ambient temperature range. features z 4.5v to 28v operating input voltage range z integrated linear regulator controller z 40 m ? internal nfet, effi ciency: up to 95% z internal soft start z each output voltage adjustable down to 0.8v z 3a continuous output current z fixed 370 khz pwm operation z cycle-by-cycle current limit z short-circuit protection z thermal shutdown z small size 4x3 dfn-12 package z independent enable input for buck and ldo applications z point of load dc/dc conversion z set top boxes z lcd monitors & tvs z cable modems z telecom/networking/datacom equipment typical application figure 1. typical application circuit lx vin bs vbias fb1 gnd en1 ldrv fb2 comp c1 22f en2 c4 1f c6 1f c5 0.1f vout1 vout1 vin c2, c3 22f x 2 r1 31.6k r2 10k l1 6.8h AOZ1214 r c 30k c c 2.2nf c7 4.7f r4 8.06k r3 10k vout2
rev. 1.0 december 2010 www.aosmd.com page 2 of 16 AOZ1214 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/qual ity/rohs_com pliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1214di -40c to +85c 4x3 dfn-12l green product pin number pin name pin function 1 lx buck regulator switching node. 2 bst buck regulator bootstrap pin. bst is the high side driver supply. connect a 0.1 f capacitor between bst and lx to form a bootstrap circuit. 3 pgnd power ground. 4 en1 enable1 input for buck regulator. en1 is active high. connect en1 to in if not used. do not leave en1 floating. 5 en2 enable2 input for linear regulator. en2 is active high. 6 fb1 buck regulator feedback input. fb1 is regulated to 0.8v. set the buck regulator output voltage using a resistive voltage divider. 7 comp buck regulator compensation pin. comp is the output of the internal transconductance error amplifier. connect a rc network between comp and gnd to compensate the control loop. 8 fb2 linear regulator feedback input. fb2 is regulate d to 0.8v. set the linear regulator output voltage using a resistive voltage divider. 9 ldrv linear regulator drive output. ldrv contro ls the gate of an external pass transistor. 10 agnd analog ground. 11 bias internal bias regulator output. connect a 1 f between bias and gnd. 12 in input supply pin. the input range is between 4.5v and 28v. lx bst pgnd en1 en2 fb1 in bias agnd ldrv fb2 comp in agnd dfn-12 (top view) 12 11 10 9 8 7 1 2 3 4 5 6
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 3 of 16 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. recommended operating conditions the device is not guaranteed to operate beyond the maximum recommended operating conditions. note: 1. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given application depends on the user's specific board design. 370khz oscillator pgnd agnd ldrv vin en2 en1 vbias fb comp comp lx bst otp ilimit pw uvp < 0.6v m control logic 5v ldo regulator uvlo & por +5v gm = 200a/v softstart 1 softstart 2 reference & bias 0.8v q1 q2 pwm comp isen eamp 0.3v + ? + ? gm = 2a/v eamp2 + ? + ? + ? + short detect comparator parameter rating supply voltage (v in ) 30v lx to gnd -0.7v to v in + 0.3v en1, en2 to gnd -0.3v to v in + 0.3v fb1, fb2 to gnd -0.3v to 6v comp to gnd -0.3v to 6v bst to gnd v lx + 6v ldrv to gnd -0.3v to 6v pg to gnd -0.3v to 30v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c parameter rating supply voltage (v in ) 4.5v to 28v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package therma l resistance 4 x 3 dfn-12 ( ja ) (1 ) 4 x 3 dfn-12 ( jc ) 64.6c/w 7.1c/w
rev. 1.0 december 2010 www.aosmd.com page 4 of 16 AOZ1214 electrical characteristics t a = 25c, v in = v en = 12v, unless otherwise specified (2) . note: 2. specification in bold indicate an ambient temperature range of -40c to + 85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 28 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.0 3.7 v v i in supply current (quiescent) i out = 0, vfb = 1.2v, v en > 2v 23 ma i off shutdown supply current v en1 = v en2 = 0v 3 20 a v fb1, 2 feedback voltage 0.788 0.8 0.812 v load regulation 0.5 % line regulation 0.1 % i fb1 feedback voltage input current 200 na enable v en1,2 en1,2 input threshold off threshold on threshold 2.5 0.6 v v v hys en1,2 input hysteresis 200 mv i en1,2 en1,2 sink/source current 50 na modulator f o frequency 315 370 425 khz d max maximum duty cycle 85 % d min minimum duty cycle 5 % g vea error amplifier voltage gain 500 v / v g ea error amplifier transconductance 200 a / v protection i lim current limit 4 5 6 a over-temperature shutdown limit t j rising t j falling 145 100 c c t ss1 soft start interval 1 6 ms t ss2 soft start interval 2 6 ms pwm output stage r ds(on) high-side switch on-resistance 40 50 m high-side switch leakage v en = 0v, v lx = 0v 10 a linear controller ldrv vout drive output high voltage vfb2 = 0.7v, ldrv iout = 20ma, iout1 = 0 4v ldrv iout drive output current vfb2 = 0.7v, iout1 = 0 10 ma under voltage threshold 0.6 v line regulation 0.5 % load regulation 1 % i fb2 fb2 leakage 150 na
rev. 1.0 december 2010 www.aosmd.com page 5 of 16 AOZ1214 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. efficiency (vin = 24v, l = 6.8h) efficiency (vin = 12v, l = 6.8h) efficiency (vin = 5v, l = 6.8h) 70% 75% 80% 85% 90% 95% 100% 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) efficiency (%) load current (a) efficiency (%) load current (a) efficiency (%) 8.0v output 5.0v output 3.3v output 70% 75% 80% 85% 90% 95% 100% 0 0.5 1.0 1.5 2.0 2.5 3.0 8.0v output 5.0v output 3.3v output 70% 75% 80% 85% 90% 95% 100% 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3v output 1.8v output frequency vs. vin (vout = 3.3v, l = 6.8h, 25c) 350 360 370 380 390 0 5 10 15 20 25 30 frequency (khz) frequency (hz) frequency vs. temperature (vin = 12v, vout = 3.3v, l = 6.8h) 300 320 340 360 380 400 420 -45 -30 -15 0 15 30 45 60 75 90 soft start time (vout = 3.3v, l = 6.8h, 25c) 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 soft start time (ms) soft start time vs. temp (vin = 12v, vout = 3.3v, l = 6.8h) 4.5 5.0 5.5 6.0 6.5 -45 -30 -15 0 15 30 45 60 75 90 soft start time (ms) minimum vin (25c) 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0.5 1.0 1.5 2.0 2.5 3.0 vin (v) uvlo vs. temp (vin = 12v, vout = 3.3v, l = 6.8h, 25c) 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 -45 -30 -15 0 15 30 45 60 75 90 uvlo (v) vin_fall 12v input 5v input 3.3v input vin_rise icc vs. temp (vin = 12v, vout = 3.3v, l = 6.8h) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -45 -30 -15 0 15 30 45 60 75 90 vfb1 vs. vin (vout = 3.3v, l = 6.8h, 25c) 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 4 6 8 10121416182022242628 current limit vs. vin (vout = 3.3v, l = 6.8h, 25c) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 4 6 8 10121416182022242628 icc (ma) vfb1 (v) current limit (a) temperature (c) temperature (c) temperature (c) vin (v) vin (v) temperature (c) load (a) vin (v) vin (v)
rev. 1.0 december 2010 www.aosmd.com page 6 of 16 AOZ1214 typical performance characteristics (continued) circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. current limit vs. temp (vin = 12v, vout = 3.3v, l = 6.8h) -45 -30 -15 0 15 30 45 60 75 90 current limit (a) vfb2 vs. temp (vin = 12v, vout = 3.3v, l = 6.8h) vfb1 vs. temp (vin = 12v, vout = 3.3v, l = 6.8h) 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 -45 -30 -15 0 15 30 45 60 75 90 vfb2 (v) vfb1 (v) 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 -45 -30 -15 0 15 30 45 60 75 90 en1,2 vs. vin (ovout = 3.3v, l = 6.8h, no load, 25c) 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 4 6 8 10121416182022242628 vin (v) en1,2 (v) en1,2 on (v) en1,2 off (v) en1,2 on en1,2 off en1,2 on vs. temp (vout = 3.3v, l = 6.8h) en1,2 off vs. temp (vout = 3.3v, l = 6.8h) 1.0 1.5 2.0 2.5 3.0 -45 -30 -15 0 15 30 45 60 75 90 24v input 12v input 5v input 1.0 1.5 2.0 2.5 3.0 -45 -30 -15 0 15 30 45 60 75 90 24v input 12v input 5v input en1,2 hysteresis vs temp (vout = 3.3v, l = 6.8h) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) en1,2 hysteresis (v) 24v input 12v input 5v input ldrv source current vs. temp (vfb2 = 0.7v, ldrv = 4v) 0 5 10 15 20 25 30 35 40 -45 -30 -15 0 15 30 45 60 75 90 ldrv source current (ma) ldrv output voltage vs. source current (fb2 = 0.7v, 25c) 0 1 2 3 4 5 0 102030405060 ldrv source current (ma) ldrv output voltage (v) 0?1.5a vo ripple 200mv/div io 1a/div 200s/div 200s/div io 1a/div vo ripple 200mv/div 1.5a?3a 6.0 5.5 5.0 4.5 4.0
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 7 of 16 detailed description the AOZ1214 is a current-mode step down regulator with integrated high side nm os switch. it operates from a 4.5v to 28v input voltage range and supplies up to 3a of load current. the duty cycle can be adjusted from 5% to 85% allowing a wide range of output voltage. features include independent enable control for buck and linear regulator, power-on reset, input under voltage lockout, fixed internal soft-start and thermal shut down. the linear regulator controller is designe d to drive an external npn power transistor or an n channel power mosfet to provide up to 1a of curr ent to an auxiliary load. the AOZ1214 is available in 4x3 dfn-12 package. enable and soft start the AOZ1214 has independent internal soft start feature to limit buck and ldo in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. when the input voltage rises to 4.0v and voltage on en1, en2 pin is high, the soft start processes of buck and linear regulator independently begin. in each soft start process, the buck or linear regulator output voltage is ramped to regulation voltage in typically 6ms. the 6ms soft start time is set internally. connect the en1, en2 pin to vi n if enable function is not used. pull en1 and en2 to gr ound will disable the buck and linear regulator independently. do not leave them open. the voltage on en1, en 2 pin must be above 2.5v to active. when voltage on en1, en2 pin falls below 0.6v, the buck and linear regulator is disabled independently. if an application circuit requires the AOZ1214 buck or linear regulator to be disabled, an open drain or open collector circuit should be used to interface to en1 or en2 pin. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the AOZ1214 integrates an internal n-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. since the n-mosfet requires a gate voltage higher than the input voltage, a boost capacitor connected between lx pin and bst pin drives the gate. the boost capacitor is charged while lx is low. an internal 10 ohm switch from lx to pgnd is used to insure that lx is pulled to pgnd even in the light load. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal trans- conductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor cu rrent is freewheeling through the schottky diode to output. switching frequency the AOZ1214 switching frequency is fixed and set by an internal oscillator. the switching frequency is set 370 khz. output voltage programming output voltage can be set by feeding back the output to the fb pin with a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r 1 with equation below. some standard value of r 1 , r 2 for most commonly used output voltage values are listed in table 1. table 1. the combination of r1 and r2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. vo (v) r 1 (k ) r 2 (k ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 12.0 140 10 v out 1 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 8 of 16 protection features the AOZ1214 has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current si gnal is also used for over current protection. since the AOZ1214 employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. the cycle by cycle current limit threshold is internally set. when the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediat ely to terminate the current duty cycle. the inductor current stop rising. the cycle by cycle current limit protection directly limits inductor peak current. the average inductor current is also limited due to the limitation on peak indu ctor current. when cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. the AOZ1214 has internal short circuit protection to protect itself from catastroph ic failure under output short circuit conditions. the fb pin voltage is proportional to the output voltage. whenever fb pin voltage is below 0.3v, the short circuit protection circuit is triggered. to prevent current limit running away, when comp pin voltage is higher than 2.1v, t he short circuit protection is also triggered. before short pr otection is triggered, there is about 1 ms blank time to prevent false trigger caused by glitch or noise. the conv erter will start up via a soft start once the short circuit condition disappears. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4.0v, the converter starts operation. when input voltage falls below 3.7v, the converter will stop switching. linear regulator the AOZ1214 contains an error amplifier which can be configured as a linear regulator controller. by adding an external follower (npn or nmos) and divider resistors as shown in figure 1, the fb2 and ldrv pins can be configured as a controller for a low dropout regulator. the ldrv pin source capab ility come from ldo inside which is capable more than 10ma of base current to the external npn transistor. the fb2 voltage is monitored by an under voltage protection circuit, which shutdown ldrv output when fb2 voltage is under 0.6v. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side nmos if the junc tion temperature exceeds 145oc. the regulator will rest art automatically under the control of soft-start circuit when the junction temperature decreases to 100oc. application information the basic AOZ1214 application circuit is shown in figure 1. component selection is explained below. buck regulator design input capacitor the input capacitor (c 1 in figure 1) must be connected to the v in pin and gnd pin of the AOZ1214 to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . v in i o fc in ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? = v o v in -------- - m =
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 9 of 16 figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high ripple current rating. depending on the application circuits, other low esr tantalum capacitor or aluminum electrolytic capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures is based on certain amount of life time. further de-rating may be necessary for practical design requirement. inductor the inductor is used to supply constant current to output when it is driven by a swit ching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is, the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduction loss. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is select ed based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacito r must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specif ication is another important factor for selecting the outp ut capacitor. in a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where; c o is output capacitor value and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum capacitor or aluminum electrolytic capacitor may also be used as output capacitors. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- + = v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- ?? ?? = v o i l esr co =
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 10 of 16 in a buck converter, out put capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. schottky diode selection the external freewheeling diode supplies the current to the inductor when the high side nmos switch is off. to reduce the losses due to the forward voltage drop and recovery of diode, schottky diode is recommended to use. the maximum reverse voltage rating of the chosen schottky diode should be greater than the maximum input voltage and size for average forward current in normal condition. average forward current can be calculated from: loop compensation the AOZ1214 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the doubl e pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole and can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. several different types of compensation network can be used for AOZ1214. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ1214, fb pin and comp pin are the inverting input and the output of internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c c is the compensation capacitor. the zero given by the external compensation network, capacitor c c and resistor r c , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover frequency is also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high due to system stability concern. when designing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. it is recommended to choose a crossover freq uency less than 30 khz. i co_rms i l 12 ---------- = i d_ave i o v in -------- - v in v out ? () = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = f c 30 khz =
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 11 of 16 the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected cr ossover frequency, f c , to calculate r c : where;o f c is desired crossover frequency, v fb is 0.8v, g ea is the error amplifier transconductance, which is 200x10 -6 a/v, and g cs is the current sense circui t transconductance, which is 5.64 a/v. the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: equation above can also be simplified to: table 2. recommended parameters an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . linear regulator design adjustable output voltage the output voltage can be set by feeding back the output to fb2 pin with a resistor divider network. in the application circuit shown in figure 1. the linear regulator output voltage can be obtained using the following equation: r4 should be less than 10 kohm to avoid bias current errors. external npn pass transistor or mosfet both transistor and mosfet c an be used as an external follower. some cautions must be noticed: 1. the transistor and mosfet should be able to supply maximum operating current for the linear regulator supply. 2. dc current gain h fe must be large enough so that the pass transistor and supply the maximum load current with 30 ma with base current. however, too big h fe may cause the ldo sensitive to current noise, and a compromised dc current gain transistor should be selected. 3. the total power dissipation should not be higher than the rated value. 4. comparing with transistor, mosfet has lower dropout voltage which is r ds(on) times the output current. but the minimum input voltage will increase to v o plus v gs while transistor is v o plus v be . linear regulator output capacitor the linear regulator requires using an output capacitor as part of the frequency compensation network, which affects the stability and high frequency response. the regulator has a finite band width. for high frequency transient loads, reco very from transient is determined by both output capacitor and the bandwidth of the regulator. a minimum output capacitor of 4.7 f is recommended to prevent oscillations and provi de good transient response. the esr value should be maintained in the range that determines the loop stability. when small signal ringing v in v o 1.2v 3.3v 5v 12v l = 1.5 h?3.3 h r c = 10k ? c c = 6.8nf l = 4.7 h?10 h r c = 30k ? c c = 2.2nf l = 6.8 h?15 h r c = 30k ? c c = 3.3nf 20v l = 1.5 h r c = 10k ? c c = 6.8nf l = 4.7 h?10 h r c = 30k ? c c = 2.2nf l = 6.8uh?15 h r c = 30k ? c c = 3.3nf r c f c v o v fb ---------- 2 c o g ea g cs ----------------------------- - = c c 1.5 2 r c f p 1 ---------------------------------- - = c c c o r l r c --------------------- = v out 2 0.8 1 r 3 r 4 ------- - + ?? ?? =
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 12 of 16 occurs with ceramics due to insufficient esr in low output voltage condition, adding esr or increasing the capacitor value improves t he stability and reduces the ringing. but too high esr is also not suggested, which will cause the zero too big a nd the phase margin is not satisfied. high esr also brings in high voltage ripple. the lower the output voltage is, the higher value esr is needed. basically, esr between 0.02 ohm and 3 ohm can make sure the circuit stable. solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, only if their capacitance and esr meet the requirements. output voltage ripple the ldo is designed to provide low output voltage noise while operating at any load. because of the existence of stray inductance and capacitance, sometimes there could be a big ripple voltage in the output which is unexpected. the following tips could decrease the ripple voltage to a lower value: 1. improve the pcb layout. signal grounds should connect to agnd to insure the noise is small. low side divider resistor connects to agnd directly. keep sensitive signal trace such as fb2 pin, ldrv pin as short as possible, and far away from noise trace; 2. adding a bypass capacitor from fb2 pin to agnd, which will lower the bandwid th of the loop. the impedance of the fb2 pin capacitor at the ripple frequency should be less than the value of r3. 3. adding a resistor r g between ldrv and base of transistor (gate of mosfet), which can structure a rc filter with the ca pacitor of base-emitter to reduce the noise. as the increasing of r g value, the noise getting smaller. considering the power dispassion of the r g , its value is often between 10 ohm and 100 ohm. 4. increasing the capacitance of output capacitor or add the esr of the output capacitor. 5. change the pass transistor to a lower h fe type (mosfet to a lower g fs type), thus the loop gain can be smaller as a sour ce follower. but the h fe and g fs should be large enough to meet the output current requirement. thermal management and layout consideration in the AOZ1214 buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacito rs, to the vin pin, to the lx pins, to the filter induct or, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the gnd pin of the AOZ1214, to the lx pins of the azo1214. current flows in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and im proves efficiency. a ground plane is recommended to connect input capacitor, output capacitor, and gnd pin of the AOZ1214. in the AOZ1214 buck regulator circuit, the three major power dissipating components are the AOZ1214, external diode and output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of inductor can be approximately calculated by output current and dcr of inductor. the power dissipation of diode is: the actual AOZ1214 juncti on temperature can be calculated with power dissipation in the AOZ1214 and thermal impedance from junction to ambient. the maximum junction tem perature of AOZ1214 is 145oc, which limits the maxi mum load current capability. the thermal performance of the AOZ1214 is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental conditions. p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 = p diode_loss i o v f 1 v o v in -------- - ? ?? ?? ?? = t junction p total_loss p inductor_loss ? () ja = t ambient ++
rev. 1.0 december 2010 www.aosmd.com page 13 of 16 AOZ1214 several layout tips are listed below for the best electric and thermal performance. figure 3 is the layout example. 1. do not use thermal relief connection to the vin and the gnd pin. pour a maximized copper area to the gnd pin and the vin pin to help thermal dissipation. 2. input capacitor should be connected to the vin pin and the gnd pin as close as possible. 3. make the current trace from lx pins to l to co to the gnd as short as possible. 4. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 5. keep sensitive signal trace such as trace connected with fb pin and comp pin far away form the lx pins. figure 3. layout example for the AOZ1214 top side bottom side
rev. 1.0 december 2010 www.aosmd.com page 14 of 16 AOZ1214 package dimensions, dfn 4x3, 12l top view side view bottom view a e d/2 index area (d/2 x e/2) seating plane e/2 a1 a3 a b 1 e l1 d1 l2 d2 l3 l3 l e1/2 e1 pin #1 ida chamfer 0.15 recommended land pattern notes: 1. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 2. the location of the terminal #1 identifier and terminal numbering conforms to jedec publication 95 spp-002. 3. dimension b applied to metallized terminal and is measured between 0.20mm and 0.35mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, dimension b should not be measured in that radius area. 4. coplanarity ddd applies to the terminals and all other bottom surface metallization. symbols a a1 a3 b d d1 d2 e e1 e l l1 l2 l3 aaa bbb ccc ddd dimensions in millimeters min. 0.80 0.00 0.20 0.83 1.86 1.45 0.30 0.61 0.21 nom. 0.90 0.02 0.20 ref. 0.23 4.00 bsc 0.985 2.015 3.00 bsc 1.60 0.50 bsc 0.40 0.715 0.315 0.30 ref. 0.15 0.10 0.10 0.08 max. 1.00 0.05 0.35 1.09 2.12 1.70 0.50 0.82 0.42 unit: mm 0.50 0.25 0.23 0.50 0.30 0.715 0.80 1.60 1.35 2.70 0.20 x 45 1.035 0.315 2.065 0.30 symbols a a1 a3 b d d1 d2 e e1 e l l1 l2 l3 aaa bbb ccc ddd dimensions in inches min. 0.031 0.000 0.008 0.033 0.073 0.057 0.012 0.024 0.008 nom. 0.035 0.001 0.008 ref. 0.009 0.157 bsc 0.039 0.079 0.118 bsc 0.063 0.020 bsc 0.016 0.028 0.012 0.012 ref. 0.006 0.004 0.004 0.003 max. 0.039 0.002 0.014 0.043 0.083 0.067 0.020 0.032 0.017
AOZ1214 rev. 1.0 december 2010 www.aosmd.com page 15 of 16 tape and reel dimensions, dfn 4x3 carrier tape reel leader / trailer & orientation tape size 12mm reel size ?330 m ?330.0 2.0 package dfn 4 x 3 (12 mm) a0 3.40 0.10 b0 4.40 0.10 k0 1.10 0.10 d0 1.50 min. d1 1.50 +0.10/-0.0 e 12.0 0.3 e1 1.75 0.10 e2 5.50 0.05 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.30 0.05 n ?79.0 1.0 trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets unit: mm unit: mm feeding direction w 12.4 +2.0/-0 w1 17.0 +2.6/-0 v r h ?13.0 0.5 k 10.5 0.2 s 2.0 0.5 g d1 p1 p2 e1 e e2 b0 k0 t a0 p0 d0 c l v r g s h w w1 k n m
rev. 1.0 december 2010 www.aosmd.com page 16 of 16 AOZ1214 part marking z1214di AOZ1214di (4 x 3 df n -12) fay w lt part nu mber code assembly lot code fab & assembly location year & w eek code as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this datasheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not authorized for use as critical components in life su pport devices or systems.

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